<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2086221</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Nov  2 22:47:27 2020</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2017.4 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>926ae7854f0745a7a5495ce6c32b52d8</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>46</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>73d14eecaefa5c46b3ddafcbe0fdd33c</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>73d14eecaefa5c46b3ddafcbe0fdd33c</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z020</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg484</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-6300HQ CPU @ 2.30GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2304 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addilaprobespopup_cancel=4</TD>
   <TD>addilaprobespopup_ok=36</TD>
   <TD>addresstreetablepanel_address_tree_table=4</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>addsrcwizard_specify_simulation_specific_hdl_files=1</TD>
   <TD>basedialog_cancel=57</TD>
   <TD>basedialog_ok=543</TD>
   <TD>basedialog_yes=42</TD>
</TR><TR ALIGN='LEFT'>   <TD>clkconfigmainpanel_expand_all=1</TD>
   <TD>cmdmsgdialog_copy_message=1</TD>
   <TD>cmdmsgdialog_ok=25</TD>
   <TD>constraintschooserpanel_create_file=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>coretreetablepanel_core_tree_table=19</TD>
   <TD>createconstraintsfilepanel_file_name=2</TD>
   <TD>creatersbportdialog_frequency=1</TD>
   <TD>creatersbportdialog_port_name=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>creatersbportdialog_type=1</TD>
   <TD>createsrcfiledialog_file_name=14</TD>
   <TD>ddrconfigmainpanel_expand_all=1</TD>
   <TD>ddrconfigtreetablepanel_ddr_config_tree_table=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugview_debug_cores_tree_table=23</TD>
   <TD>debugwizard_chipscope_tree_table=69</TD>
   <TD>debugwizard_input_pipe_stages=2</TD>
   <TD>debugwizard_sample_of_data_depth=44</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugwizard_select_clock_domain=58</TD>
   <TD>debugwizard_set_probe_type=5</TD>
   <TD>definemodulesdialog_new_source_files=7</TD>
   <TD>filesetpanel_file_set_panel_tree=561</TD>
</TR><TR ALIGN='LEFT'>   <TD>flownavigatortreepanel_flow_navigator_tree=346</TD>
   <TD>gensettingmainpanel_expand_all=1</TD>
   <TD>gensettingtreetablepanel_gen_setting_tree_table=1</TD>
   <TD>gictreetablepanel_gic_tree_table=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>graphicalview_zoom_fit=15</TD>
   <TD>graphicalview_zoom_in=198</TD>
   <TD>graphicalview_zoom_out=114</TD>
   <TD>hardwaredashboardoptionspanel_close_dashboard_options=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwaredashboardview_show_dashboard_options=1</TD>
   <TD>hardwareilawaveformview_run_trigger_for_this_ila_core=79</TD>
   <TD>hardwareilawaveformview_run_trigger_immediate_for_this_ila_core=10</TD>
   <TD>hardwareilawaveformview_stop_trigger_for_this_ila_core=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwareilawaveformview_toggle_auto_re_trigger_mode=105</TD>
   <TD>hardwaretreepanel_hardware_tree_table=2</TD>
   <TD>hpopuptitle_close=6</TD>
   <TD>ilaprobetablepanel_add_probe=19</TD>
</TR><TR ALIGN='LEFT'>   <TD>ilaprobetablepanel_remove_selected_probe=9</TD>
   <TD>ilaprobetablepanel_remove_selected_probes=3</TD>
   <TD>ilaprobetablepanel_set_trigger_condition_to_global=2</TD>
   <TD>labtoolsmenu_name=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_edit=6</TD>
   <TD>mainmenumgr_export=174</TD>
   <TD>mainmenumgr_file=248</TD>
   <TD>mainmenumgr_import=22</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_open_recent_file=110</TD>
   <TD>mainmenumgr_open_recent_project=106</TD>
   <TD>mainwintoolbarmgr_select_or_save_window_layout=1</TD>
   <TD>miotablepagepanel_mio_table=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>miotablepagepanel_mio_table_parameter=1</TD>
   <TD>msgtreepanel_discard_user_created_messages=2</TD>
   <TD>msgtreepanel_message_severity=4</TD>
   <TD>msgtreepanel_message_view_tree=16</TD>
</TR><TR ALIGN='LEFT'>   <TD>navigabletimingreporttab_timing_report_navigation_tree=3</TD>
   <TD>netlisttreeview_netlist_tree=6</TD>
   <TD>newexporthardwaredialog_include_bitstream=9</TD>
   <TD>opentargetwizard_connect_to=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_add_sources=9</TD>
   <TD>pacommandnames_auto_assign_address=2</TD>
   <TD>pacommandnames_auto_connect_ports=10</TD>
   <TD>pacommandnames_auto_connect_target=51</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_update_hier=8</TD>
   <TD>pacommandnames_create_top_hdl=4</TD>
   <TD>pacommandnames_debug_wizard=42</TD>
   <TD>pacommandnames_export_hardware=55</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_generate_composite_file=4</TD>
   <TD>pacommandnames_goto_netlist_design=2</TD>
   <TD>pacommandnames_launch_hardware=57</TD>
   <TD>pacommandnames_open_target_wizard=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_regenerate_layout=4</TD>
   <TD>pacommandnames_save_design=40</TD>
   <TD>pacommandnames_set_as_top=3</TD>
   <TD>pacommandnames_toggle_view_nav=32</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_validate_rsb_design=3</TD>
   <TD>pacommandnames_zoom_out=5</TD>
   <TD>paviews_dashboard=51</TD>
   <TD>paviews_device=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_system=2</TD>
   <TD>pickclockdomainnetdialog_clock_domain_nets_tree=27</TD>
   <TD>planaheadtab_show_flow_navigator=32</TD>
   <TD>probesview_probes_tree=194</TD>
</TR><TR ALIGN='LEFT'>   <TD>probevaluetablepanel_text_field=2</TD>
   <TD>programdebugtab_program_device=7</TD>
   <TD>programdebugtab_refresh_device=9</TD>
   <TD>programfpgadialog_program=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>progressdialog_cancel=1</TD>
   <TD>projecttab_close_design=1</TD>
   <TD>projecttab_reload=2</TD>
   <TD>quickhelp_help=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_delete=4</TD>
   <TD>rdicommands_properties=3</TD>
   <TD>rdiviews_waveform_viewer=517</TD>
   <TD>removesourcesdialog_also_delete=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>rsbexternalinterfaceproppanels_associated_clock_port=2</TD>
   <TD>rsbexternalinterfaceproppanels_name=5</TD>
   <TD>rsbexternalportproppanels_associated_clock_port=1</TD>
   <TD>rsbexternalportproppanels_name=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>rungadget_run_gadget_tabbed_pane=2</TD>
   <TD>rungadget_show_error_and_critical_warning_messages=1</TD>
   <TD>rungadget_show_warning_and_error_messages_in_messages=1</TD>
   <TD>selectmenu_highlight=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>simpleoutputproductdialog_close_dialog_unsaved_changes_will=1</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=6</TD>
   <TD>srcchooserpanel_create_file=14</TD>
   <TD>srcchoosertable_src_chooser_table=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcmenu_ip_hierarchy=7</TD>
   <TD>stalemoreaction_out_of_date_details=1</TD>
   <TD>syntheticagettingstartedview_recent_projects=11</TD>
   <TD>systembuildermenu_create_port=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>systembuilderview_add_ip=6</TD>
   <TD>systembuilderview_expand_collapse=6</TD>
   <TD>targetchooserpanel_target_chooser_table=2</TD>
   <TD>taskbanner_close=106</TD>
</TR><TR ALIGN='LEFT'>   <TD>tclconsoleview_clear_all_output_in_tcl_console=1</TD>
   <TD>tclconsoleview_tcl_console_code_editor=6</TD>
   <TD>triggercapturecontrolpanel_window_data_depth=2</TD>
   <TD>triggersetuppanel_table=121</TD>
</TR><TR ALIGN='LEFT'>   <TD>waveformnametree_waveform_name_tree=483</TD>
   <TD>waveformoptionsview_show_grid_lines=3</TD>
   <TD>waveformview_add=34</TD>
   <TD>waveformview_remove_selected=8</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=9</TD>
   <TD>autoassignaddress=2</TD>
   <TD>autoconnectport=10</TD>
   <TD>autoconnecttarget=51</TD>
</TR><TR ALIGN='LEFT'>   <TD>createblockdesign=2</TD>
   <TD>createtophdl=4</TD>
   <TD>customizecore=2</TD>
   <TD>customizersbblock=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>debugwizardcmdhandler=42</TD>
   <TD>editdelete=8</TD>
   <TD>editproperties=3</TD>
   <TD>launchopentarget=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>launchprogramfpga=7</TD>
   <TD>managecompositetargets=4</TD>
   <TD>newexporthardware=55</TD>
   <TD>newlaunchhardware=57</TD>
</TR><TR ALIGN='LEFT'>   <TD>newproject=1</TD>
   <TD>openhardwaremanager=55</TD>
   <TD>openrecenttarget=2</TD>
   <TD>recustomizecore=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>refreshdevice=7</TD>
   <TD>regeneratersblayout=4</TD>
   <TD>runbitgen=50</TD>
   <TD>runimplementation=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>runsynthesis=62</TD>
   <TD>runtrigger=79</TD>
   <TD>runtriggerimmediate=10</TD>
   <TD>savedesign=40</TD>
</TR><TR ALIGN='LEFT'>   <TD>settopnode=3</TD>
   <TD>showview=9</TD>
   <TD>stoptrigger=11</TD>
   <TD>toggleviewnavigator=32</TD>
</TR><TR ALIGN='LEFT'>   <TD>validatersbdesign=3</TD>
   <TD>viewlayoutcmd=1</TD>
   <TD>viewtaskimplementation=2</TD>
   <TD>viewtasksynthesis=48</TD>
</TR><TR ALIGN='LEFT'>   <TD>zoomout=10</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=12</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=5</TD>
   <TD>export_simulation_ies=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=5</TD>
   <TD>export_simulation_questa=5</TD>
   <TD>export_simulation_riviera=5</TD>
   <TD>export_simulation_vcs=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=5</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=12</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=9</TD>
   <TD>totalsynthesisruns=9</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf=130</TD>
    <TD>bufg=4</TD>
    <TD>carry4=127</TD>
    <TD>fdce=224</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdpe=34</TD>
    <TD>fdre=1793</TD>
    <TD>fdse=80</TD>
    <TD>gnd=109</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=1</TD>
    <TD>lut1=243</TD>
    <TD>lut2=142</TD>
    <TD>lut3=392</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=383</TD>
    <TD>lut5=357</TD>
    <TD>lut6=348</TD>
    <TD>mmcme2_adv=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf=1</TD>
    <TD>ps7=1</TD>
    <TD>ramb18e1=1</TD>
    <TD>ramb36e1=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramd32=20</TD>
    <TD>rams32=6</TD>
    <TD>srl16e=21</TD>
    <TD>srlc32e=47</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=103</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf=130</TD>
    <TD>bufg=4</TD>
    <TD>carry4=127</TD>
    <TD>fdce=224</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdpe=34</TD>
    <TD>fdre=1793</TD>
    <TD>fdse=80</TD>
    <TD>gnd=109</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=2</TD>
    <TD>lut1=243</TD>
    <TD>lut2=142</TD>
    <TD>lut3=392</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=383</TD>
    <TD>lut5=357</TD>
    <TD>lut6=348</TD>
    <TD>mmcme2_adv=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf=1</TD>
    <TD>ps7=1</TD>
    <TD>ram32m=3</TD>
    <TD>ram32x1d=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1=1</TD>
    <TD>ramb36e1=7</TD>
    <TD>srl16e=21</TD>
    <TD>srlc32e=47</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=103</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=8</TD>
    <TD>bram_ports_total=16</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=1906</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=68</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bdsource=USER</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>maxhierdepth=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numblks=13</TD>
    <TD>numhdlrefblks=0</TD>
    <TD>numhierblks=6</TD>
    <TD>numhlsblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numnonxlnxblks=0</TD>
    <TD>numpkgbdblks=0</TD>
    <TD>numreposblks=7</TD>
    <TD>numsysgenblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>synth_mode=OOC_per_IP</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=BlockDiagram</TD>
    <TD>x_ipname=design_1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.00.a</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_crossbar_v2_1_16_axi_crossbar/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_axi_addr_width=32</TD>
    <TD>c_axi_aruser_width=1</TD>
    <TD>c_axi_awuser_width=1</TD>
    <TD>c_axi_buser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_data_width=32</TD>
    <TD>c_axi_id_width=1</TD>
    <TD>c_axi_protocol=2</TD>
    <TD>c_axi_ruser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_supports_user_signals=0</TD>
    <TD>c_axi_wuser_width=1</TD>
    <TD>c_connectivity_mode=0</TD>
    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_addr_width=0x0000001000000010</TD>
    <TD>c_m_axi_base_addr=0x0000000043c000000000000041200000</TD>
    <TD>c_m_axi_read_connectivity=0x0000000100000001</TD>
    <TD>c_m_axi_read_issuing=0x0000000100000001</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_secure=0x0000000000000000</TD>
    <TD>c_m_axi_write_connectivity=0x0000000100000001</TD>
    <TD>c_m_axi_write_issuing=0x0000000100000001</TD>
    <TD>c_num_addr_ranges=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_master_slots=2</TD>
    <TD>c_num_slave_slots=1</TD>
    <TD>c_r_register=1</TD>
    <TD>c_s_axi_arb_priority=0x00000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_base_id=0x00000000</TD>
    <TD>c_s_axi_read_acceptance=0x00000001</TD>
    <TD>c_s_axi_single_thread=0x00000001</TD>
    <TD>c_s_axi_thread_id_width=0x00000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_write_acceptance=0x00000001</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_crossbar</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_gpio/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_all_inputs=1</TD>
    <TD>c_all_inputs_2=0</TD>
    <TD>c_all_outputs=0</TD>
    <TD>c_all_outputs_2=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dout_default=0x00000000</TD>
    <TD>c_dout_default_2=0x00000000</TD>
    <TD>c_family=zynq</TD>
    <TD>c_gpio2_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_gpio_width=1</TD>
    <TD>c_interrupt_present=1</TD>
    <TD>c_is_dual=0</TD>
    <TD>c_s_axi_addr_width=9</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_data_width=32</TD>
    <TD>c_tri_default=0xFFFFFFFF</TD>
    <TD>c_tri_default_2=0xFFFFFFFF</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=17</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipname=axi_gpio</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipversion=2.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_protocol_converter_v2_1_15_axi_protocol_converter/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_axi_addr_width=32</TD>
    <TD>c_axi_aruser_width=1</TD>
    <TD>c_axi_awuser_width=1</TD>
    <TD>c_axi_buser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_data_width=32</TD>
    <TD>c_axi_id_width=12</TD>
    <TD>c_axi_ruser_width=1</TD>
    <TD>c_axi_supports_read=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_supports_user_signals=0</TD>
    <TD>c_axi_supports_write=1</TD>
    <TD>c_axi_wuser_width=1</TD>
    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ignore_id=0</TD>
    <TD>c_m_axi_protocol=2</TD>
    <TD>c_s_axi_protocol=1</TD>
    <TD>c_translation_mode=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=15</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_protocol_converter</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_protocol_converter_v2_1_15_axi_protocol_converter/2</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_axi_addr_width=32</TD>
    <TD>c_axi_aruser_width=1</TD>
    <TD>c_axi_awuser_width=1</TD>
    <TD>c_axi_buser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_data_width=64</TD>
    <TD>c_axi_id_width=6</TD>
    <TD>c_axi_ruser_width=1</TD>
    <TD>c_axi_supports_read=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_supports_user_signals=0</TD>
    <TD>c_axi_supports_write=1</TD>
    <TD>c_axi_wuser_width=1</TD>
    <TD>c_family=zynq</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_ignore_id=0</TD>
    <TD>c_m_axi_protocol=1</TD>
    <TD>c_s_axi_protocol=0</TD>
    <TD>c_translation_mode=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=15</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=axi_protocol_converter</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v5_4_3_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=20.000</TD>
    <TD>clkin2_period=10.0</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=pll_clk</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=true</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=true</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>fifo_generator_v13_2_1/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_add_ngc_constraint=0</TD>
    <TD>c_application_type_axis=0</TD>
    <TD>c_application_type_rach=0</TD>
    <TD>c_application_type_rdch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_application_type_wach=0</TD>
    <TD>c_application_type_wdch=0</TD>
    <TD>c_application_type_wrch=0</TD>
    <TD>c_axi_addr_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_aruser_width=1</TD>
    <TD>c_axi_awuser_width=1</TD>
    <TD>c_axi_buser_width=1</TD>
    <TD>c_axi_data_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_id_width=1</TD>
    <TD>c_axi_len_width=8</TD>
    <TD>c_axi_lock_width=1</TD>
    <TD>c_axi_ruser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_type=1</TD>
    <TD>c_axi_wuser_width=1</TD>
    <TD>c_axis_tdata_width=8</TD>
    <TD>c_axis_tdest_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axis_tid_width=1</TD>
    <TD>c_axis_tkeep_width=1</TD>
    <TD>c_axis_tstrb_width=1</TD>
    <TD>c_axis_tuser_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axis_type=0</TD>
    <TD>c_common_clock=0</TD>
    <TD>c_count_type=0</TD>
    <TD>c_data_count_width=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_default_value=BlankString</TD>
    <TD>c_din_width=64</TD>
    <TD>c_din_width_axis=1</TD>
    <TD>c_din_width_rach=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_din_width_rdch=64</TD>
    <TD>c_din_width_wach=1</TD>
    <TD>c_din_width_wdch=64</TD>
    <TD>c_din_width_wrch=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dout_rst_val=0</TD>
    <TD>c_dout_width=64</TD>
    <TD>c_en_safety_ckt=1</TD>
    <TD>c_enable_rlocs=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_enable_rst_sync=1</TD>
    <TD>c_error_injection_type=0</TD>
    <TD>c_error_injection_type_axis=0</TD>
    <TD>c_error_injection_type_rach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_error_injection_type_rdch=0</TD>
    <TD>c_error_injection_type_wach=0</TD>
    <TD>c_error_injection_type_wdch=0</TD>
    <TD>c_error_injection_type_wrch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_full_flags_rst_val=1</TD>
    <TD>c_has_almost_empty=1</TD>
    <TD>c_has_almost_full=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axi_aruser=0</TD>
    <TD>c_has_axi_awuser=0</TD>
    <TD>c_has_axi_buser=0</TD>
    <TD>c_has_axi_id=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axi_rd_channel=1</TD>
    <TD>c_has_axi_ruser=0</TD>
    <TD>c_has_axi_wr_channel=1</TD>
    <TD>c_has_axi_wuser=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axis_tdata=1</TD>
    <TD>c_has_axis_tdest=0</TD>
    <TD>c_has_axis_tid=0</TD>
    <TD>c_has_axis_tkeep=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axis_tlast=0</TD>
    <TD>c_has_axis_tready=1</TD>
    <TD>c_has_axis_tstrb=0</TD>
    <TD>c_has_axis_tuser=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_backup=0</TD>
    <TD>c_has_data_count=0</TD>
    <TD>c_has_data_counts_axis=0</TD>
    <TD>c_has_data_counts_rach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_data_counts_rdch=0</TD>
    <TD>c_has_data_counts_wach=0</TD>
    <TD>c_has_data_counts_wdch=0</TD>
    <TD>c_has_data_counts_wrch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_int_clk=0</TD>
    <TD>c_has_master_ce=0</TD>
    <TD>c_has_meminit_file=0</TD>
    <TD>c_has_overflow=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_prog_flags_axis=0</TD>
    <TD>c_has_prog_flags_rach=0</TD>
    <TD>c_has_prog_flags_rdch=0</TD>
    <TD>c_has_prog_flags_wach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_prog_flags_wdch=0</TD>
    <TD>c_has_prog_flags_wrch=0</TD>
    <TD>c_has_rd_data_count=1</TD>
    <TD>c_has_rd_rst=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_rst=1</TD>
    <TD>c_has_slave_ce=0</TD>
    <TD>c_has_srst=0</TD>
    <TD>c_has_underflow=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_valid=0</TD>
    <TD>c_has_wr_ack=0</TD>
    <TD>c_has_wr_data_count=0</TD>
    <TD>c_has_wr_rst=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_implementation_type=2</TD>
    <TD>c_implementation_type_axis=1</TD>
    <TD>c_implementation_type_rach=1</TD>
    <TD>c_implementation_type_rdch=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_implementation_type_wach=1</TD>
    <TD>c_implementation_type_wdch=1</TD>
    <TD>c_implementation_type_wrch=1</TD>
    <TD>c_init_wr_pntr_val=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_interface_type=0</TD>
    <TD>c_memory_type=1</TD>
    <TD>c_mif_file_name=BlankString</TD>
    <TD>c_msgon_val=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_optimization_mode=0</TD>
    <TD>c_overflow_low=0</TD>
    <TD>c_power_saving_mode=0</TD>
    <TD>c_preload_latency=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_preload_regs=1</TD>
    <TD>c_prim_fifo_type=4kx9</TD>
    <TD>c_prim_fifo_type_axis=1kx18</TD>
    <TD>c_prim_fifo_type_rach=512x36</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prim_fifo_type_rdch=1kx36</TD>
    <TD>c_prim_fifo_type_wach=512x36</TD>
    <TD>c_prim_fifo_type_wdch=1kx36</TD>
    <TD>c_prim_fifo_type_wrch=512x36</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_thresh_assert_val=4</TD>
    <TD>c_prog_empty_thresh_assert_val_axis=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_rach=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_rdch=1022</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_thresh_assert_val_wach=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_wdch=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_wrch=1022</TD>
    <TD>c_prog_empty_thresh_negate_val=5</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_type=0</TD>
    <TD>c_prog_empty_type_axis=0</TD>
    <TD>c_prog_empty_type_rach=0</TD>
    <TD>c_prog_empty_type_rdch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_type_wach=0</TD>
    <TD>c_prog_empty_type_wdch=0</TD>
    <TD>c_prog_empty_type_wrch=0</TD>
    <TD>c_prog_full_thresh_assert_val=4095</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_thresh_assert_val_axis=1023</TD>
    <TD>c_prog_full_thresh_assert_val_rach=1023</TD>
    <TD>c_prog_full_thresh_assert_val_rdch=1023</TD>
    <TD>c_prog_full_thresh_assert_val_wach=1023</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_thresh_assert_val_wdch=1023</TD>
    <TD>c_prog_full_thresh_assert_val_wrch=1023</TD>
    <TD>c_prog_full_thresh_negate_val=4094</TD>
    <TD>c_prog_full_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_type_axis=0</TD>
    <TD>c_prog_full_type_rach=0</TD>
    <TD>c_prog_full_type_rdch=0</TD>
    <TD>c_prog_full_type_wach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_type_wdch=0</TD>
    <TD>c_prog_full_type_wrch=0</TD>
    <TD>c_rach_type=0</TD>
    <TD>c_rd_data_count_width=13</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rd_depth=4096</TD>
    <TD>c_rd_freq=1</TD>
    <TD>c_rd_pntr_width=12</TD>
    <TD>c_rdch_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_slice_mode_axis=0</TD>
    <TD>c_reg_slice_mode_rach=0</TD>
    <TD>c_reg_slice_mode_rdch=0</TD>
    <TD>c_reg_slice_mode_wach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_slice_mode_wdch=0</TD>
    <TD>c_reg_slice_mode_wrch=0</TD>
    <TD>c_select_xpm=0</TD>
    <TD>c_synchronizer_stage=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_underflow_low=0</TD>
    <TD>c_use_common_overflow=0</TD>
    <TD>c_use_common_underflow=0</TD>
    <TD>c_use_default_settings=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_dout_rst=1</TD>
    <TD>c_use_ecc=0</TD>
    <TD>c_use_ecc_axis=0</TD>
    <TD>c_use_ecc_rach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_ecc_rdch=0</TD>
    <TD>c_use_ecc_wach=0</TD>
    <TD>c_use_ecc_wdch=0</TD>
    <TD>c_use_ecc_wrch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_embedded_reg=0</TD>
    <TD>c_use_fifo16_flags=0</TD>
    <TD>c_use_fwft_data_count=1</TD>
    <TD>c_use_pipeline_reg=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_valid_low=0</TD>
    <TD>c_wach_type=0</TD>
    <TD>c_wdch_type=0</TD>
    <TD>c_wr_ack_low=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_data_count_width=13</TD>
    <TD>c_wr_depth=4096</TD>
    <TD>c_wr_depth_axis=1024</TD>
    <TD>c_wr_depth_rach=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_depth_rdch=1024</TD>
    <TD>c_wr_depth_wach=16</TD>
    <TD>c_wr_depth_wdch=1024</TD>
    <TD>c_wr_depth_wrch=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_freq=1</TD>
    <TD>c_wr_pntr_width=12</TD>
    <TD>c_wr_pntr_width_axis=10</TD>
    <TD>c_wr_pntr_width_rach=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_pntr_width_rdch=10</TD>
    <TD>c_wr_pntr_width_wach=4</TD>
    <TD>c_wr_pntr_width_wdch=10</TD>
    <TD>c_wr_pntr_width_wrch=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_response_latency=1</TD>
    <TD>c_wrch_type=0</TD>
    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=1</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=fifo_generator</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=13.2</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>proc_sys_reset/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_aux_reset_high=0</TD>
    <TD>c_aux_rst_width=4</TD>
    <TD>c_ext_reset_high=0</TD>
    <TD>c_ext_rst_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_num_bus_rst=1</TD>
    <TD>c_num_interconnect_aresetn=1</TD>
    <TD>c_num_perp_aresetn=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_perp_rst=1</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>x_ipcorerevision=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=proc_sys_reset</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5.5_user_configuration/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>pcw_apu_clk_ratio_enable=6:2:1</TD>
    <TD>pcw_apu_peripheral_freqmhz=666.666666</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_armpll_ctrl_fbdiv=40</TD>
    <TD>pcw_can0_grp_clk_enable=0</TD>
    <TD>pcw_can0_peripheral_clksrc=External</TD>
    <TD>pcw_can0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_can0_peripheral_freqmhz=-1</TD>
    <TD>pcw_can1_grp_clk_enable=0</TD>
    <TD>pcw_can1_peripheral_clksrc=External</TD>
    <TD>pcw_can1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_can1_peripheral_freqmhz=-1</TD>
    <TD>pcw_can_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_can_peripheral_freqmhz=100</TD>
    <TD>pcw_cpu_cpu_pll_freqmhz=1333.333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_cpu_peripheral_clksrc=ARM PLL</TD>
    <TD>pcw_crystal_peripheral_freqmhz=33.333333</TD>
    <TD>pcw_dci_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_dci_peripheral_freqmhz=10.159</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_ddr_pll_freqmhz=1066.667</TD>
    <TD>pcw_ddr_hpr_to_critical_priority_level=15</TD>
    <TD>pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)</TD>
    <TD>pcw_ddr_lpr_to_critical_priority_level=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_ddr_port0_hpr_enable=0</TD>
    <TD>pcw_ddr_port1_hpr_enable=0</TD>
    <TD>pcw_ddr_port2_hpr_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_port3_hpr_enable=0</TD>
    <TD>pcw_ddr_write_to_critical_priority_level=2</TD>
    <TD>pcw_ddrpll_ctrl_fbdiv=32</TD>
    <TD>pcw_enet0_grp_mdio_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet0_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_enet0_peripheral_enable=0</TD>
    <TD>pcw_enet0_peripheral_freqmhz=1000 Mbps</TD>
    <TD>pcw_enet0_reset_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet1_grp_mdio_enable=0</TD>
    <TD>pcw_enet1_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_enet1_peripheral_enable=0</TD>
    <TD>pcw_enet1_peripheral_freqmhz=1000 Mbps</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet1_reset_enable=0</TD>
    <TD>pcw_enet_reset_polarity=Active Low</TD>
    <TD>pcw_fclk0_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk1_peripheral_clksrc=IO PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fclk2_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk3_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fpga0_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga1_peripheral_freqmhz=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga2_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga3_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga_fclk0_enable=1</TD>
    <TD>pcw_fpga_fclk1_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga_fclk2_enable=0</TD>
    <TD>pcw_fpga_fclk3_enable=0</TD>
    <TD>pcw_ftm_cti_in0=DISABLED</TD>
    <TD>pcw_ftm_cti_in1=DISABLED</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ftm_cti_in2=DISABLED</TD>
    <TD>pcw_ftm_cti_in3=DISABLED</TD>
    <TD>pcw_ftm_cti_out0=DISABLED</TD>
    <TD>pcw_ftm_cti_out1=DISABLED</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ftm_cti_out2=DISABLED</TD>
    <TD>pcw_ftm_cti_out3=DISABLED</TD>
    <TD>pcw_gpio_emio_gpio_enable=0</TD>
    <TD>pcw_gpio_mio_gpio_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_gpio_peripheral_enable=0</TD>
    <TD>pcw_i2c0_grp_int_enable=0</TD>
    <TD>pcw_i2c0_peripheral_enable=0</TD>
    <TD>pcw_i2c0_reset_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_i2c1_grp_int_enable=0</TD>
    <TD>pcw_i2c1_peripheral_enable=0</TD>
    <TD>pcw_i2c1_reset_enable=0</TD>
    <TD>pcw_i2c_reset_polarity=Active Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_io_io_pll_freqmhz=1800.000</TD>
    <TD>pcw_iopll_ctrl_fbdiv=54</TD>
    <TD>pcw_irq_f2p_mode=DIRECT</TD>
    <TD>pcw_m_axi_gp0_freqmhz=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_m_axi_gp1_freqmhz=10</TD>
    <TD>pcw_nand_cycles_t_ar=1</TD>
    <TD>pcw_nand_cycles_t_clr=1</TD>
    <TD>pcw_nand_cycles_t_rc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nand_cycles_t_rea=1</TD>
    <TD>pcw_nand_cycles_t_rr=1</TD>
    <TD>pcw_nand_cycles_t_wc=11</TD>
    <TD>pcw_nand_cycles_t_wp=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nand_grp_d8_enable=0</TD>
    <TD>pcw_nand_peripheral_enable=0</TD>
    <TD>pcw_nor_cs0_t_ceoe=1</TD>
    <TD>pcw_nor_cs0_t_pc=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs0_t_rc=11</TD>
    <TD>pcw_nor_cs0_t_tr=1</TD>
    <TD>pcw_nor_cs0_t_wc=11</TD>
    <TD>pcw_nor_cs0_t_wp=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs0_we_time=0</TD>
    <TD>pcw_nor_cs1_t_ceoe=1</TD>
    <TD>pcw_nor_cs1_t_pc=1</TD>
    <TD>pcw_nor_cs1_t_rc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs1_t_tr=1</TD>
    <TD>pcw_nor_cs1_t_wc=11</TD>
    <TD>pcw_nor_cs1_t_wp=1</TD>
    <TD>pcw_nor_cs1_we_time=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_grp_a25_enable=0</TD>
    <TD>pcw_nor_grp_cs0_enable=0</TD>
    <TD>pcw_nor_grp_cs1_enable=0</TD>
    <TD>pcw_nor_grp_sram_cs0_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_grp_sram_cs1_enable=0</TD>
    <TD>pcw_nor_grp_sram_int_enable=0</TD>
    <TD>pcw_nor_peripheral_enable=0</TD>
    <TD>pcw_nor_sram_cs0_t_ceoe=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs0_t_pc=1</TD>
    <TD>pcw_nor_sram_cs0_t_rc=11</TD>
    <TD>pcw_nor_sram_cs0_t_tr=1</TD>
    <TD>pcw_nor_sram_cs0_t_wc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs0_t_wp=1</TD>
    <TD>pcw_nor_sram_cs0_we_time=0</TD>
    <TD>pcw_nor_sram_cs1_t_ceoe=1</TD>
    <TD>pcw_nor_sram_cs1_t_pc=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs1_t_rc=11</TD>
    <TD>pcw_nor_sram_cs1_t_tr=1</TD>
    <TD>pcw_nor_sram_cs1_t_wc=11</TD>
    <TD>pcw_nor_sram_cs1_t_wp=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs1_we_time=0</TD>
    <TD>pcw_override_basic_clock=0</TD>
    <TD>pcw_pcap_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_pcap_peripheral_freqmhz=200</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_pjtag_peripheral_enable=0</TD>
    <TD>pcw_preset_bank0_voltage=LVCMOS 3.3V</TD>
    <TD>pcw_preset_bank1_voltage=LVCMOS 1.8V</TD>
    <TD>pcw_qspi_grp_fbclk_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_grp_io1_enable=0</TD>
    <TD>pcw_qspi_grp_single_ss_enable=0</TD>
    <TD>pcw_qspi_grp_ss1_enable=0</TD>
    <TD>pcw_qspi_internal_highaddress=0xFCFFFFFF</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_qspi_peripheral_enable=0</TD>
    <TD>pcw_qspi_peripheral_freqmhz=200</TD>
    <TD>pcw_s_axi_acp_freqmhz=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_gp0_freqmhz=10</TD>
    <TD>pcw_s_axi_gp1_freqmhz=10</TD>
    <TD>pcw_s_axi_hp0_data_width=64</TD>
    <TD>pcw_s_axi_hp0_freqmhz=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_hp1_data_width=64</TD>
    <TD>pcw_s_axi_hp1_freqmhz=10</TD>
    <TD>pcw_s_axi_hp2_data_width=64</TD>
    <TD>pcw_s_axi_hp2_freqmhz=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_hp3_data_width=64</TD>
    <TD>pcw_s_axi_hp3_freqmhz=10</TD>
    <TD>pcw_sd0_grp_cd_enable=1</TD>
    <TD>pcw_sd0_grp_cd_io=MIO 10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd0_grp_pow_enable=0</TD>
    <TD>pcw_sd0_grp_wp_enable=0</TD>
    <TD>pcw_sd0_peripheral_enable=1</TD>
    <TD>pcw_sd0_sd0_io=MIO 40 .. 45</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd1_grp_cd_enable=0</TD>
    <TD>pcw_sd1_grp_pow_enable=0</TD>
    <TD>pcw_sd1_grp_wp_enable=0</TD>
    <TD>pcw_sd1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sdio_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_sdio_peripheral_freqmhz=100</TD>
    <TD>pcw_smc_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_smc_peripheral_freqmhz=100</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi0_grp_ss0_enable=0</TD>
    <TD>pcw_spi0_grp_ss1_enable=0</TD>
    <TD>pcw_spi0_grp_ss2_enable=0</TD>
    <TD>pcw_spi0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi1_grp_ss0_enable=0</TD>
    <TD>pcw_spi1_grp_ss1_enable=0</TD>
    <TD>pcw_spi1_grp_ss2_enable=0</TD>
    <TD>pcw_spi1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_spi_peripheral_freqmhz=166.666666</TD>
    <TD>pcw_tpiu_peripheral_clksrc=External</TD>
    <TD>pcw_tpiu_peripheral_freqmhz=200</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_trace_grp_16bit_enable=0</TD>
    <TD>pcw_trace_grp_2bit_enable=0</TD>
    <TD>pcw_trace_grp_32bit_enable=0</TD>
    <TD>pcw_trace_grp_4bit_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_trace_grp_8bit_enable=0</TD>
    <TD>pcw_trace_peripheral_enable=0</TD>
    <TD>pcw_ttc0_clk0_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk0_peripheral_freqmhz=133.333333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc0_clk1_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk1_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc0_clk2_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk2_peripheral_freqmhz=133.333333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc0_peripheral_enable=0</TD>
    <TD>pcw_ttc1_clk0_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc1_clk0_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_clk1_peripheral_clksrc=CPU_1X</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc1_clk1_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_clk2_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc1_clk2_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc_peripheral_freqmhz=50</TD>
    <TD>pcw_uart0_baud_rate=115200</TD>
    <TD>pcw_uart0_grp_full_enable=0</TD>
    <TD>pcw_uart0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uart1_baud_rate=115200</TD>
    <TD>pcw_uart1_grp_full_enable=0</TD>
    <TD>pcw_uart1_peripheral_enable=1</TD>
    <TD>pcw_uart1_uart1_io=MIO 12 .. 13</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uart_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_uart_peripheral_freqmhz=100</TD>
    <TD>pcw_uiparam_ddr_adv_enable=0</TD>
    <TD>pcw_uiparam_ddr_al=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_bank_addr_count=3</TD>
    <TD>pcw_uiparam_ddr_bl=8</TD>
    <TD>pcw_uiparam_ddr_board_delay0=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay1=0.25</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_board_delay2=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay3=0.25</TD>
    <TD>pcw_uiparam_ddr_bus_width=32 Bit</TD>
    <TD>pcw_uiparam_ddr_cl=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_0_package_length=61.0905</TD>
    <TD>pcw_uiparam_ddr_clock_0_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_1_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_1_package_length=61.0905</TD>
    <TD>pcw_uiparam_ddr_clock_1_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_2_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_2_package_length=61.0905</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_3_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_3_package_length=61.0905</TD>
    <TD>pcw_uiparam_ddr_clock_3_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_stop_en=0</TD>
    <TD>pcw_uiparam_ddr_col_addr_count=10</TD>
    <TD>pcw_uiparam_ddr_cwl=6</TD>
    <TD>pcw_uiparam_ddr_device_capacity=4096 MBits</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_0_package_length=64.1705</TD>
    <TD>pcw_uiparam_ddr_dq_0_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_1_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_1_package_length=63.686</TD>
    <TD>pcw_uiparam_ddr_dq_1_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_2_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_2_package_length=68.46</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_3_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_3_package_length=105.4895</TD>
    <TD>pcw_uiparam_ddr_dq_3_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_0_package_length=68.4725</TD>
    <TD>pcw_uiparam_ddr_dqs_0_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_1_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_1_package_length=71.086</TD>
    <TD>pcw_uiparam_ddr_dqs_1_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_2_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_2_package_length=66.794</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_3_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_3_package_length=108.7385</TD>
    <TD>pcw_uiparam_ddr_dqs_3_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dram_width=16 Bits</TD>
    <TD>pcw_uiparam_ddr_ecc=Disabled</TD>
    <TD>pcw_uiparam_ddr_enable=1</TD>
    <TD>pcw_uiparam_ddr_freq_mhz=533.333333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_high_temp=Normal (0-85)</TD>
    <TD>pcw_uiparam_ddr_memory_type=DDR 3</TD>
    <TD>pcw_uiparam_ddr_partno=MT41J256M16 RE-125</TD>
    <TD>pcw_uiparam_ddr_row_addr_count=15</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_speed_bin=DDR3_1066F</TD>
    <TD>pcw_uiparam_ddr_t_faw=40.0</TD>
    <TD>pcw_uiparam_ddr_t_ras_min=35.0</TD>
    <TD>pcw_uiparam_ddr_t_rc=48.91</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_t_rcd=7</TD>
    <TD>pcw_uiparam_ddr_t_rp=7</TD>
    <TD>pcw_uiparam_ddr_train_data_eye=1</TD>
    <TD>pcw_uiparam_ddr_train_read_gate=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_train_write_level=1</TD>
    <TD>pcw_uiparam_ddr_use_internal_vref=0</TD>
    <TD>pcw_usb0_peripheral_enable=0</TD>
    <TD>pcw_usb0_peripheral_freqmhz=60</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_usb0_reset_enable=0</TD>
    <TD>pcw_usb1_peripheral_enable=0</TD>
    <TD>pcw_usb1_peripheral_freqmhz=60</TD>
    <TD>pcw_usb1_reset_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_usb_reset_polarity=Active Low</TD>
    <TD>pcw_use_cross_trigger=0</TD>
    <TD>pcw_use_m_axi_gp0=1</TD>
    <TD>pcw_use_m_axi_gp1=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_s_axi_acp=0</TD>
    <TD>pcw_use_s_axi_gp0=0</TD>
    <TD>pcw_use_s_axi_gp1=0</TD>
    <TD>pcw_use_s_axi_hp0=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_s_axi_hp1=0</TD>
    <TD>pcw_use_s_axi_hp2=0</TD>
    <TD>pcw_use_s_axi_hp3=0</TD>
    <TD>pcw_wdt_peripheral_clksrc=CPU_1X</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_wdt_peripheral_enable=0</TD>
    <TD>pcw_wdt_peripheral_freqmhz=133.333333</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5_5_processing_system7/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_dm_width=4</TD>
    <TD>c_dq_width=32</TD>
    <TD>c_dqs_width=4</TD>
    <TD>c_emio_gpio_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_emio_enet0=0</TD>
    <TD>c_en_emio_enet1=0</TD>
    <TD>c_en_emio_pjtag=0</TD>
    <TD>c_en_emio_trace=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fclk_clk0_buf=TRUE</TD>
    <TD>c_fclk_clk1_buf=FALSE</TD>
    <TD>c_fclk_clk2_buf=FALSE</TD>
    <TD>c_fclk_clk3_buf=FALSE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_gp0_en_modifiable_txn=1</TD>
    <TD>c_gp1_en_modifiable_txn=1</TD>
    <TD>c_include_acp_trans_check=0</TD>
    <TD>c_include_trace_buffer=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_irq_f2p_mode=DIRECT</TD>
    <TD>c_m_axi_gp0_enable_static_remap=0</TD>
    <TD>c_m_axi_gp0_id_width=12</TD>
    <TD>c_m_axi_gp0_thread_id_width=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_gp1_enable_static_remap=0</TD>
    <TD>c_m_axi_gp1_id_width=12</TD>
    <TD>c_m_axi_gp1_thread_id_width=12</TD>
    <TD>c_mio_primitive=54</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_f2p_intr_inputs=1</TD>
    <TD>c_package_name=clg484</TD>
    <TD>c_ps7_si_rev=PRODUCTION</TD>
    <TD>c_s_axi_acp_aruser_val=31</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_acp_awuser_val=31</TD>
    <TD>c_s_axi_acp_id_width=3</TD>
    <TD>c_s_axi_gp0_id_width=6</TD>
    <TD>c_s_axi_gp1_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_hp0_data_width=64</TD>
    <TD>c_s_axi_hp0_id_width=6</TD>
    <TD>c_s_axi_hp1_data_width=64</TD>
    <TD>c_s_axi_hp1_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_hp2_data_width=64</TD>
    <TD>c_s_axi_hp2_id_width=6</TD>
    <TD>c_s_axi_hp3_data_width=64</TD>
    <TD>c_s_axi_hp3_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_trace_buffer_clock_delay=12</TD>
    <TD>c_trace_buffer_fifo_size=128</TD>
    <TD>c_trace_internal_width=2</TD>
    <TD>c_trace_pipeline_width=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_axi_nonsecure=0</TD>
    <TD>c_use_default_acp_user_val=0</TD>
    <TD>c_use_m_axi_gp0=1</TD>
    <TD>c_use_m_axi_gp1=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_acp=0</TD>
    <TD>c_use_s_axi_gp0=0</TD>
    <TD>c_use_s_axi_gp1=0</TD>
    <TD>c_use_s_axi_hp0=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_hp1=0</TD>
    <TD>c_use_s_axi_hp2=0</TD>
    <TD>c_use_s_axi_hp3=0</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>use_trace_data_edge_detector=0</TD>
    <TD>x_ipcorerevision=6</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=processing_system7</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.5</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>ps2pl_para_v1_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_s0_axi_addr_width=4</TD>
    <TD>c_s0_axi_data_width=32</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=2</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=user</TD>
    <TD>x_ipname=ps2pl_para</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_cdc_async_rst/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>def_val=1&apos;b0</TD>
    <TD>dest_sync_ff=2</TD>
    <TD>init_sync_ff=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>inv_def_val=1&apos;b1</TD>
    <TD>iptotal=3</TD>
    <TD>rst_active_high=1</TD>
    <TD>version=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_cdc_gray/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>dest_sync_ff=2</TD>
    <TD>init_sync_ff=0</TD>
    <TD>iptotal=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>reg_output=1</TD>
    <TD>sim_assert_chk=0</TD>
    <TD>sim_lossless_gray_chk=0</TD>
    <TD>version=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>width=12</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_cdc_single/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>dest_sync_ff=5</TD>
    <TD>init_sync_ff=0</TD>
    <TD>iptotal=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>sim_assert_chk=0</TD>
    <TD>src_input_reg=0</TD>
    <TD>version=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_cdc_sync_rst/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>def_val=1&apos;b1</TD>
    <TD>dest_sync_ff=5</TD>
    <TD>init=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>init_sync_ff=0</TD>
    <TD>iptotal=2</TD>
    <TD>sim_assert_chk=0</TD>
    <TD>version=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>check-3=1</TD>
    <TD>reqp-1839=20</TD>
    <TD>reqp-1840=7</TD>
    <TD>rtstat-10=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>pdrc-190=1</TD>
    <TD>timing-17=306</TD>
    <TD>timing-27=1</TD>
    <TD>timing-4=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>timing-6=1</TD>
    <TD>timing-7=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_propagation=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vid=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=8to11 (8 to 11 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>bram=0.004766</TD>
    <TD>clocks=0.003982</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_clock_activity=Medium</TD>
    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_io_activity=Low</TD>
    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
</TR><TR ALIGN='LEFT'>    <TD>devstatic=0.146718</TD>
    <TD>die=xc7z020clg484-2</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=1.650183</TD>
</TR><TR ALIGN='LEFT'>    <TD>effective_thetaja=11.5</TD>
    <TD>enable_probability=0.990000</TD>
    <TD>family=zynq</TD>
    <TD>ff_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>flow_state=routed</TD>
    <TD>heatsink=none</TD>
    <TD>i/o=0.000366</TD>
    <TD>input_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>junction_temp=45.7 (C)</TD>
    <TD>logic=0.001258</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mgtvccaux_dynamic_current=0.000000</TD>
    <TD>mgtvccaux_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtvccaux_total_current=0.000000</TD>
    <TD>mgtvccaux_voltage=1.800000</TD>
    <TD>mmcm=0.105026</TD>
    <TD>netlist_net_matched=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=1.796902</TD>
    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_toggle=12.500000</TD>
    <TD>package=clg484</TD>
    <TD>pct_clock_constrained=3.000000</TD>
    <TD>pct_inputs_defined=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
    <TD>ps7=1.533122</TD>
    <TD>ram_enable=50.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>ram_write=50.000000</TD>
    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>signals=0.001663</TD>
    <TD>simulation_file=None</TD>
    <TD>speedgrade=-2</TD>
    <TD>static_prob=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>temp_grade=commercial</TD>
    <TD>thetajb=7.4 (C/W)</TD>
    <TD>thetasa=0.0 (C/W)</TD>
    <TD>toggle_rate=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_board_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=11.5</TD>
    <TD>user_junc_temp=45.7 (C)</TD>
    <TD>user_thetajb=7.4 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_thetasa=0.0 (C/W)</TD>
    <TD>vccadc_dynamic_current=0.000000</TD>
    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccaux_dynamic_current=0.058291</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.015599</TD>
    <TD>vccaux_total_current=0.073890</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccbram_dynamic_current=0.000421</TD>
    <TD>vccbram_static_current=0.001450</TD>
    <TD>vccbram_total_current=0.001870</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccint_dynamic_current=0.011376</TD>
    <TD>vccint_static_current=0.015873</TD>
    <TD>vccint_total_current=0.027249</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_voltage=1.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco18_dynamic_current=0.000000</TD>
    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco33_dynamic_current=0.000103</TD>
    <TD>vcco33_static_current=0.001000</TD>
    <TD>vcco33_total_current=0.001103</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_voltage=3.300000</TD>
    <TD>vcco_ddr_dynamic_current=0.456904</TD>
    <TD>vcco_ddr_static_current=0.002000</TD>
    <TD>vcco_ddr_total_current=0.458904</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_ddr_voltage=1.500000</TD>
    <TD>vcco_mio0_dynamic_current=0.000458</TD>
    <TD>vcco_mio0_static_current=0.001000</TD>
    <TD>vcco_mio0_total_current=0.001458</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio0_voltage=1.800000</TD>
    <TD>vcco_mio1_dynamic_current=0.000875</TD>
    <TD>vcco_mio1_static_current=0.001000</TD>
    <TD>vcco_mio1_total_current=0.001875</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio1_voltage=1.800000</TD>
    <TD>vccpaux_dynamic_current=0.050335</TD>
    <TD>vccpaux_static_current=0.010330</TD>
    <TD>vccpaux_total_current=0.060665</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpaux_voltage=1.800000</TD>
    <TD>vccpint_dynamic_current=0.726085</TD>
    <TD>vccpint_static_current=0.031423</TD>
    <TD>vccpint_total_current=0.757507</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpint_voltage=1.000000</TD>
    <TD>vccpll_dynamic_current=0.015934</TD>
    <TD>vccpll_static_current=0.003000</TD>
    <TD>vccpll_total_current=0.018934</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpll_voltage=1.800000</TD>
    <TD>version=2017.4</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=4</TD>
    <TD>bufgctrl_util_percentage=12.50</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=72</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=16</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=8</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=16</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=4</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>mmcme2_adv_util_percentage=25.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=4</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=220</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=1</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=1</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=1</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=140</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=7.5</TD>
    <TD>block_ram_tile_util_percentage=5.36</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=280</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=1</TD>
    <TD>ramb18_util_percentage=0.36</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1_only_used=1</TD>
    <TD>ramb36_fifo_available=140</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_util_percentage=5.00</TD>
    <TD>ramb36e1_only_used=7</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf_functional_category=IO</TD>
    <TD>bibuf_used=130</TD>
    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=119</TD>
    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=224</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=34</TD>
    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=1569</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=79</TD>
    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=125</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=127</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=349</TD>
    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=347</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=287</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=289</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ps7_functional_category=Specialized Resource</TD>
    <TD>ps7_used=1</TD>
    <TD>ramb18e1_functional_category=Block Memory</TD>
    <TD>ramb18e1_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=7</TD>
    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=20</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=6</TD>
    <TD>srl16e_functional_category=Distributed Memory</TD>
    <TD>srl16e_used=21</TD>
</TR><TR ALIGN='LEFT'>    <TD>srlc32e_functional_category=Distributed Memory</TD>
    <TD>srlc32e_used=47</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=26600</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=0</TD>
    <TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=13300</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=14</TD>
    <TD>lut_as_logic_available=53200</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=1284</TD>
    <TD>lut_as_logic_util_percentage=2.41</TD>
    <TD>lut_as_memory_available=17400</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=78</TD>
    <TD>lut_as_memory_util_percentage=0.45</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=106400</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=1906</TD>
    <TD>register_as_flip_flop_util_percentage=1.79</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=106400</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=53200</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=1362</TD>
    <TD>slice_luts_util_percentage=2.56</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=106400</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=1906</TD>
    <TD>slice_registers_util_percentage=1.79</TD>
</TR><TR ALIGN='LEFT'>    <TD>fully_used_lut_ff_pairs_fixed=1.79</TD>
    <TD>fully_used_lut_ff_pairs_used=166</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=14</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=53200</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=1284</TD>
    <TD>lut_as_logic_util_percentage=2.41</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=17400</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=78</TD>
    <TD>lut_as_memory_util_percentage=0.45</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=64</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=64</TD>
    <TD>lut_ff_pairs_with_one_unused_flip_flop_used=577</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=577</TD>
    <TD>lut_ff_pairs_with_one_unused_lut_output_used=611</TD>
    <TD>lut_flip_flop_pairs_available=53200</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_used=807</TD>
    <TD>lut_flip_flop_pairs_util_percentage=1.52</TD>
    <TD>slice_available=13300</TD>
    <TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_used=592</TD>
    <TD>slice_util_percentage=4.45</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=367</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=225</TD>
    <TD>unique_control_sets_used=98</TD>
    <TD>using_o5_and_o6_fixed=98</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=4</TD>
    <TD>using_o5_output_only_fixed=4</TD>
    <TD>using_o5_output_only_used=2</TD>
    <TD>using_o6_output_only_fixed=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_used=58</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>actual_expansions=2447548</TD>
    <TD>bogomips=0</TD>
    <TD>bram18=1</TD>
    <TD>bram36=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
    <TD>bufr=0</TD>
    <TD>congestion_level=0</TD>
    <TD>ctrls=98</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsp=0</TD>
    <TD>effort=2</TD>
    <TD>estimated_expansions=2302650</TD>
    <TD>ff=1906</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=4</TD>
    <TD>high_fanout_nets=2</TD>
    <TD>iob=2</TD>
    <TD>lut=1430</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=4000</TD>
    <TD>nets=5558</TD>
    <TD>pins=25685</TD>
    <TD>pll=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>router_runtime=0.000000</TD>
    <TD>router_timing_driven=1</TD>
    <TD>threads=2</TD>
    <TD>timing_constraints_exist=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7z020clg484-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:51s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=559.641MB</TD>
    <TD>memory_peak=898.238MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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